This invention relates to the fabrication of integrated circuits wherein a mask pattern is imaged onto a semiconductor wafer and more particularly to the alignment of such a mask and wafer.
In the manufacture of integrated circuits, the various devices and circuit connections are formed using a photoresist layer to protect the semiconductor substrate except in the areas where processing, such as etching or metal deposition, is desired to occur.
The photoresist layer is formed by coating the substrate with a layer of resist and then patternwise exposing the resist by passing ultraviolet light through the apertures of a pattern mask. The light causes the resist layer in the light struck areas to either harden, in the case of a negative resist, or to degrade, in the case of positive resist. The unhardened or degraded areas are then removed by a developer to expose portions of the substrate for processing. The pattern masks are usually formed of a transparent substrate with a pattern opaque areas of, for example, iron oxide or chromium formed on one surface. There are generally three types of resist printing: contact printing, proximity printing, and projection printing.
Typically, in integrated circuit fabrication utilizing the techniques described above, a multiplicity of masks with different configurations are consecutively imaged at the same location of the substrate. Between the successive imagings at the same location the substrate is subjected to the desired physical and chemical changes. Thus, a passive and/or active element is obtained which is known by the name of integrated circuit.
The accuracy with which integrated circuits are manufactured has to satisfy increasingly exacting requirements. This requires that the location at which successive masks are to be imaged on the substrate should be defined with ever increasing accuracy. Deviations greater than for example 1 micron may be prohibitive. Therefore, some means to accurately align each successive mask with the wafer substrate is usually provided.
Automatic systems to achieve alignment of mask and wafer have been proposed, but these systems are very complex and relatively slow in operation. Alternatively, faster manual systems are utilized wherein an operator positions the mask and wafer, typically such that alignment marks on the mask and wafer are somehow superimposed indicating alignment. Such an aligned condition is monitored by the operator visually by means of a microscope. For example, U.S. Pat. Nos. 4,193,687 and 3,861,798 to Reekstin et al. and Kobayashi et al. respectively, both patents incorporated herein by reference, disclose the use of alignment mark patterns on the mask and wafer which may be superimposed to produce a particular moire pattern indicating alignment. These techniques however have serious drawbacks shared by other manual alignment systems. In particular, these prior techniques require the operator to differentiate between particular moire patterns, a laborious, slow process causing fatigue and eye strain.